1. Field of the Invention
The present invention relates to a circuit device, and in particular, to a device and method to generate a variable duty cycle clock using matched delay lines.
2. Description of the Related Art
Analog PLL (Phase Locked Logic) is the most popular circuit for generating a variable duty cycle clock. However, the PLL circuit transforms all signals (such as timing signals) into voltage signals, so all related analog circuits in the PLL circuit have to be redesigned for different duty cycle clocks and cause a large power loss. In addition, the PLL circuit has a signal feedback effect during signal transformation processes, so a long oscillation time and a long recovery time are also inevitable. In practice, for a high-frequency circuit, the oscillation time and the recovery time of the PLL circuit can be more than 500 clocks, which is an incredibly long time.